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(R)
EP220 & EP224 Classic EPLDs
Data Sheet
May 1995, ver. 1
Features
s
s s s s s
s s s s s
High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells - Combinatorial speeds as low as 7.5 ns - Counter frequencies of up to 100 MHz - Pipelined data rates of up to 115 MHz - Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time Replacement or upgrade for 16V8/20V8 PAL and GAL devices Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14 dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224 Macrocells independently programmable for both registered and combinatorial logic Programmable inversion control supporting active-high or activelow outputs Low power consumption - Typical ICC = 90 mA at 25 MHz (for -7A speed grades) - Quarter-power mode (ICC = 40 mA) - Programmable zero-power mode with typical ICC = 50 A (for -10A and -12 speed grades) Programmable Security Bit for total protection of proprietary designs Low output skew for Clock driver applications 100% generically tested to provide 100% programming yield Software and programming support from Altera and a wide range of third-party tools Available in windowed ceramic and one-time-programmable (OTP) plastic packages - 20-pin plastic J-lead package (PLCC) - 20-pin ceramic and plastic dual in-line packages (CerDIP and PDIP) - 24-pin PDIP - 28-pin PLCC
General Description
The EPROM-based EP220 and EP224 devices feature a flexible I/O architecture and implement 150 usable (300 available) gates of custom user logic functions. EP220 and EP224 devices can be used as upgrades for high-speed bipolar programmable logic devices (PLDs) or for 74-series LS and CMOS (SSI and MSI) logic devices in high-performance microcomputer systems.
Altera Corporation
A-ds-220/224-01
1
EP220 & EP224 Classic EPLDs
Compared to bipolar devices of equivalent speed, the EP220 and EP224 offer lower power consumption, faster input-to-nonregistered-output delay (tPD) in combinatorial mode, and higher counter frequencies in registered applications. This added performance supports faster state machine designs compared to bipolar devices, and provides additional timing margin for existing designs. The EP220 and EP224 are ideal for high-volume manufacturing of high-performance systems. These devices improve performance and decrease system noise, power consumption, and heat generation.
Functional Description
Figure 1 shows block diagrams of the EP220 and EP224 device architectures. The EP220 has 10 dedicated inputs and 8 I/O pins; the EP224 has 14 dedicated inputs and 8 I/O pins.
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Altera Corporation
EP220 & EP224 Classic EPLDs
Figure 1. EP220 & EP224 Block Diagram
Numbers in parentheses refer to the pin-out number.
EP220
Global Clock
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
(1) (2) (3) (4) (5) (6) (7) (8) (9) Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 I/O (19) I/O (18) I/O (17) I/O (16) I/O (15) I/O (14) I/O (13) I/O (12)
Global Bus
INPUT (11)
EP224
Global Clock
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
(1) (2) (3) (4) (5) (6) (7) (8) (9) Macrocell 1 Macrocell 2 Macrocell 3 Macrocell 4 Macrocell 5 Macrocell 6 Macrocell 7 Macrocell 8 I/O (22) I/O (21) I/O (20) I/O (19) I/O (18) I/O (17) I/O (16) I/O (15)
Global Bus
INPUT (10) INPUT (11) INPUT (13) INPUT (14) INPUT (23)
The EP220 and EP224 architecture is based on a sum-of-products, programmable-AND/fixed-OR structure. Each macrocell can be individually programmed for combinatorial or registered output. An inversion option allows each output to be configured for active-high or active-low operation. Each I/O pin can be programmed to function as an input, output, or bidirectional pin. The EP220 and EP224 device architecture offers the following features:
s s
Macrocells High-frequency, low-skew global Clock
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Altera Corporation
EP220 & EP224 Classic EPLDs
Macrocells
Each macrocell includes a product-term block with 8 AND product terms feeding an OR gate. One product term is dedicated to the Output Enable (OE) control of the tri-state buffer. The global logic array allows each product term to connect to the true or complement of each input--36 inputs for the EP220, 44 inputs for the EP224--and I/O feedback signal. See Figure 2.
Figure 2. EP220 & EP224 Macrocell
Output Enable
D
Q
CLK Inversion Control Programmable Register
Feedback to Logic Array Pin, I/O, and Macrocell Feedback
Feedback Select
Macrocells can be individually configured for registered or combinatorial operation, providing a mixed-mode operation not available in fixedarchitecture PAL devices. When registered output is selected, feedback from the register to the logic array bypasses the output buffer. When combinatorial output is selected, feedback comes from the I/O pin through the output buffer, and can be used for bidirectional I/O. Unlike PAL and GAL devices, all eight outputs on the EP220 and EP224 allow a combinatorial feedback signal from the I/O pin to feed the logic array. Data is clocked into the macrocell's D register on the rising edge of the global Clock.
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Altera Corporation
EP220 & EP224 Classic EPLDs
The XOR gate can implement active-high or active-low logic, and can use DeMorgan's inversion to reduce the number of product terms needed to implement a function. If the EP220 and EP224 register outputs do not require an OE signal, the internal product term can hold the output in an enabled state; if a global OE signal is required, any input can be dedicated to the task, and all eight product terms can be programmed accordingly.
High-Frequency, Low-Skew Global Clock
EP220 and EP224 devices have extremely low output-pin skew: registered output skew (tOCR) is typically less than 300 ps; combinatorial output skew (tOSC) is typically less than 400 ps. This low output-skew rate makes EP220 and EP224 devices ideal for high-frequency system Clock applications, including Intel Pentium microprocessors, 486-based PCs, and PCI bus designs.
PLD Compatibility
The EP220 and EP224 devices are a logical superset of most high-speed, 24-pin PAL/GAL devices. Industry-standard JEDEC Files from compatible devices can be programmed into EP220 or EP224 devices. Table 1 summarizes some of the devices that can be replaced or upgraded with EP220 and EP224 devices.
Table 1. EP220- and EP224-Compatible Devices (Part 1 of 4)
PAL/GAL Vendor
Advanced Micro Devices
PAL/GAL Device
PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8 PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8
Altera Replacement Device
EP220-7
Speed Grade
-7
EP224-7
EP220-10
-10
EP224-10
Altera Corporation
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EP220 & EP224 Classic EPLDs
Table 1. EP220- and EP224-Compatible Devices (Part 2 of 4)
PAL/GAL Vendor
Advanced Micro Devices (continued)
PAL/GAL Device
PAL16L8D PAL16R8D PAL16R8-7 PALCE16V8 PAL20L8-10 PAL20R8-10 PAL20R8-7 PALCE20V8 PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8
Altera Replacement Device
EP220-10A
Speed Grade
-10A
EP224-10A
EP220-12
-12
EP224-12
Lattice Semiconductor Corp.
GAL16V8B GAL20V8B GAL16V8A GAL16V8B GAL20V8A GAL20V8B
EP220-7 EP224-7 EP220-10 EP224-10 EP220-7 EP220-10
-7 -10
National Semiconductor
PAL16L8 PAL16R8 PAL16L8 PAL16R8 GAL16V8A PAL20L8 PAL20R8 GAL20V8A PAL16L8D PAL16R8D GAL16V8A PAL20L8D PAL20R8D GAL20V8A
-7 -10
EP224-10
EP220-10A
-10A
EP224-10A
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Altera Corporation
EP220 & EP224 Classic EPLDs
Table 1. EP220- and EP224-Compatible Devices (Part 3 of 4)
PAL/GAL Vendor
National Semiconductor (continued)
PAL/GAL Device
PAL16L8 PAL16R8 GAL16V8A PAL20L8 PAL20R8 GAL20V8A
Altera Replacement Device
EP220-12
Speed Grade
-12
EP224-12
Philips Semiconductor
PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8 PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8 PLUS16L8D PLUS16R8D PLUS16R8-7 PLUS20L8-10 PLUS20R8-10 PLUS20R8-7 PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8-
EP220-7 EP224-7 EP220-10 EP224-10 EP220-10A
-7
-10
-10A
EP224-10A
EP220-12 EP224-12 EP220-7 EP224-7 EP220-10 EP224-10 EP220-10A
-12
Texas Instruments, Inc.
TIBPAL16L8 TIBPAL20L8 TIBPAL16L8 TIBPAL20L8 TIBPAL16L8-10 TIBPAL16R8-10 TIBPAL16R8-7 TIBPAL20L8-10 TIBPAL20R8-10 TIBPAL20R8-7
-7 -10 -10A
EP224-10A
Altera Corporation
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EP220 & EP224 Classic EPLDs
Table 1. EP220- and EP224-Compatible Devices (Part 4 of 4)
PAL/GAL Vendor
Texas Instruments, Inc. (continued)
PAL/GAL Device
TIBPAL16L8 TIBPAL16R6 TIBPAL16R8 TIBPAL20L8 TIBPAL20R6 TIBPAL20R8
Altera Replacement Device
EP220-12
Speed Grade
-12
EP224-12
Power-On Characteristics Design Security
The EP220 and EP224 inputs and outputs respond a maximum of 1 s after VCC power-up (VCC = 4.75 V), or after a power-loss/power-up sequence. All macrocells that are programmed as registers are set to a logic low on power-up. EP220 and EP224 devices contain a programmable Security Bit that controls access to the data programmed into the device. When this bit is turned on, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security, because programmed data within EPROM cells is invisible. The Security Bit that controls this function, as well as all other program data, is reset when a device is erased. The -10A and -12 speed grades of the EP220 and EP224 devices contain a programmable Turbo Bit to control the automatic power-down feature that enables the low-standby-power mode (I CC). When the Turbo Bit is turned on, the low-standby-power mode is disabled. All AC values are tested with the Turbo Bit turned on. When the device is operating with the Turbo Bit turned off (non-turbo mode), a non-turbo adder must be added to the appropriate AC parameter to determine worst-case timing. The non-turbo adder is specified in the "AC Operating Conditions" tables in this data sheet. EP220 and EP224 devices are fully functionally tested and guaranteed. Complete testing of each programmable EPROM configuration element and all internal logic elements ensures 100% programming yield. Figure 3 shows AC test conditions.
Turbo Bit
Generic Testing
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Altera Corporation
EP220 & EP224 Classic EPLDs
Figure 3. EP220 & EP224 AC Test Circuits
Power-supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast groundcurrent transients normally occur as the device outputs discharge the load capacitances. When these transients flow through the parasitic inductance between the device ground pin and the test-system ground, significant reductions in observable noise immunity can result. Numbers in parentheses are for the EP224 device.
VCC 165 (330 ) Device Output to Test System
120 (200 )
C1 (includes JIG capacitance)
Test programs are used and then erased during the early stages of the device production flow. EPROM-based devices in one-timeprogrammable, windowless packages also contain on-board logic test circuitry to allow verification of function and AC specifications during the production flow.
Software & Programming Support f
The EP220 is supported by the Altera MAX+PLUS II development software, Altera programming hardware, and third-party hardware. Both the EP220 and EP224 are supported by the Altera PLDshell Plus design software, third-party logic compilers (e.g., ABEL, CUPL, PLDesigner, LOG/IC, and iPLS II), and third-party programming hardware (e.g., Data I/O). For more information on software support with PLDshell Plus, go to the PLDshell Plus/PLDasm User's Guide (available from the Altera Literature Department). For more information on MAX+PLUS II, go to the MAX+PLUS II Programmable Logic Development System & Software Data Sheet in the Altera 1995 Data Book , or refer to MAX+PLUS II Help. Go to the Programming Hardware Data Sheet and the Programming Hardware Manufacturers Data Sheet in the Altera 1995 Data Book for information on Altera and third-party programming hardware support.
Altera Corporation
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EP220 & EP224 Classic EPLDs
Figure 4 shows the typical supply current (ICC) versus frequency for EP220 and EP224 devices.
Figure 4. EP220 & EP224 ICC vs. Frequency
100
ICC Active (mA) Typ.
70
-7A Speed Grade
VCC = 5.0 V TA = 25 C
40
Turbo -10A and -12 Speed Grades Non-Turbo
10
20 40 60
80
100
Frequency (MHz)
Figure 5 shows the output drive characteristics of EP220 and EP224 I/O pins.
Figure 5. EP220 & EP224 Output Drive Characteristics
100
Output Current (mA)
80
IOL
60
40
VCC = 5.0 V TA = 25 C IOH
IO
20
1
2
3
4
5
VO Output Voltage (V)
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Altera Corporation
EP220 & EP224 Classic EPLDs
Absolute Maximum Ratings
Symbol
VCC VI TSTG TAMB
Note (1)
Conditions
Note (2) Notes (2), (3) Note (4)
Parameter
Supply voltage DC input voltage Storage temperature Ambient temperature
Min
-2.0 -0.5 -65 -10
Max
7.0 VCC + 0.5 150 85
Unit
V V C C
Recommended Operating Conditions
Symbol
VCC VIN VO TA TA tR tF Input voltage Output voltage Operating temperature Operating temperature Input rise time Input fall time For commercial use For industrial use
Parameter
Supply voltage
Conditions
5.0-V operation
Min
4.75 0 0 0 -40
Max
5.25 VCC VCC 70 85 500 500
Unit
V V V C C ns ns
DC Operating Conditions
Symbol
VIH VIL VOH VOL II IOZ ISC
Note (5)
Conditions
Note (6) Note (6)
IOH = -4.0 mA DC, VCC = Min. -7A, -7, -10: IOL = 24 mA DC, VCC = Min. -10A, -12: IOL = 12 mA DC, VCC = Min. VCC = Max., GND < VIN < VCC VCC = Max., GND < VOUT < VCC VCC = Max., VOUT = 0.5 V, Note (7) -10 -10 -30
Parameter
High-level input voltage Low-level input voltage High-level TTL output voltage Low-level output voltage Input leakage current Tri-state output leakage current Output short-circuit current
Min
2.0 -0.3 2.4
Max
VCC + 0.3 0.8 0.45 10 10 120
Unit
V V V V A A mA
Capacitance
Symbol
CIN COUT CCLK CVPP
Notes (5), (8)
Parameter Conditions
VIN = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VOUT = 0 V, f = 1.0 MHz VPP on pin 11 (EP220) and pin 13 (EP224), f = 1.0 MHz
Min
Max
6 8 8 10
Unit
pF pF pF pF
Input capacitance I/O capacitance Clock pin capacitance VPP pin capacitance
Altera Corporation
11
EP220 & EP224 Classic EPLDs
ICC Supply Current: EP220-7A & EP224-7A
Symbol
ICC3
Note (5)
Conditions
fIN = 25 MHz, Note (9) fIN = 100 MHz, Note (9)
Parameter
VCC supply current
Min
Max
90 115
Unit
mA mA
ICC Supply Current: EP220-10A, EP224-10A, EP220-12 & EP224-12
Symbol
ICC1 ICC2 ICC3
Note (5)
Min Max
500 5 50 60
Parameter
VCC supply current (non-turbo) VCC supply current (non-turbo) VCC supply current (turbo, active)
Conditions
Standby mode, Note (9) VCC = Max., VIN = VCC or GND, no load, fIN = 1 MHz, Notes (9), (10) fIN = 15 MHz, Note (9) fIN = 80 MHz, Note (9)
Unit
A mA mA mA
ICC Supply Current: EP220-7, EP224-7, EP220-10 & EP224-10
Symbol
ICC1 ICC3
Note (5)
Min Max
90 105 115 135
Parameter
VCC supply current (standby) VCC supply current (active)
Conditions
fIN = 25 MHz, Note (9) fIN = 74 MHz, Note (9) fIN = 25 MHz, Note (9) fIN = 74 MHz, Note (9)
Unit
A mA mA mA
Notes to tables:
See Operating Requirements for Altera Devices in the Altera 1995 Data Book. Voltage with respect to ground. Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Under bias. Extended temperature versions are also available. (5) Operating conditions: TA = 0 C to 70 C, VCC = 5.0 V 5% for commercial use. TA = -40 C to 85 C, VCC = 5.0 V 10% for industrial use. (6) Absolute values with respect to device GND; all over- and undershoots due to system or tester noise are included. (7) For -7A, -10A, -12 speed grades for EP220 and EP224 devices: maximum DC IOL (all 8 outputs) = 64 mA. For -7, -10 speed grades for EP220 and EP224 devices: test 1 output at a time; test duration should not exceed 1 s. (8) These values are measured during initial characterization. VCC = Max., VIN = VCC or GND. (9) Measured with a device programmed as an 8-bit counter. (10) When the Turbo Bit is not set (non-turbo mode), an EP220 or EP224 device enters standby mode if no logic transitions occur for approximately 75 ns after the last transition. (1) (2) (3)
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Altera Corporation
EP220 & EP224 Classic EPLDs
AC Operating Conditions: -7A, -10A, & -12 Speed Grades Combinatorial Mode
Symbol
tPD1 tPD2 tPZX tPXZ tOSR tOSC
Note (1)
EP220-10A EP224-10A EP220-12 EP224-12 Non-Turbo Adder
EP220-7A EP224-7A
Parameter
Input to non-registered output, Note (3) I/O to non-registered output, Note (3) Input or I/O to output enable, Note (4) Input or I/O to output disable, Note (4) Register-mode output to output skew Combinatorial-mode output to output skew
Min Max Min Max Min Max
7.5 7.5 9 9 300 400 10 10 12 10 12 12 12 12 -
Note (2) Units
20 20 20 20 ns ns ns ns ps ps
Synchronous Clock Mode
Symbol
fMAX fCNT1 fCNT2 tSU1 tH tCO1 tCO2 tCNT tCL tCH tCP
EP220-7A EP224-7A
EP220-10A EP224-10A
EP220-12 EP224-12
Non-Turbo Adder
Parameter
Maximum frequency (pipelined), no feedback, Note (3) Maximum counter frequency, external feedback, Note (3) Maximum counter frequency, internal feedback, Note (3) Input or I/O setup time to global clock Input or I/O hold time from global clock Global clock to output delay, Note (3) Global clock to output delay through combinatorial macrocell Minimum global clock period, Note (3) Clock low time Clock high time Clock period
Min Max Min Max Min Max Note (2)
115 100 115 4.5 0 5.5 10 10 4 4 10 4 4 9 111 80 100 7 0 5.5 13 10 5 5 11 90.9 66 83.3 9 0 6 15 12 20 0 0 20 20 0 0 0
Units
MHz MHz MHz ns ns ns ns ns ns ns ns
Notes to tables:
(1) (2) (3) (4)
Operating conditions: V CC = 5 V 5%, T A = 0 C to 70 C for commercial use. V CC = 5 V 5%, T A = -40 C to 85 C for industrial use. If the device enters standby mode and remains inactive for approximately 75 ns, increase the time by the amount shown. For EP220-10A, EP220-12, and EP224-10A, EP224-12 devices only. Measured with all outputs switching. The tPZX and tPXZ parameters are measured at 0.5 V from steady-state voltage that is driven by the specified output load. The tPXZ parameter is measured with CL = 5 pF and with all eight outputs switching.
Altera Corporation
13
EP220 & EP224 Classic EPLDs
AC Operating Conditions: -7 & -10 Speed Grades Combinatorial Mode
Symbol
tPD1 tPD2 tPZX tPXZ tOSR tOSC
Note (1)
EP220-7 EP224-7 EP220-10 EP224-10
Parameter
Input or I/O to non-registered output, inversion on, Note (2) Input or I/O to non-registered output, inversion off, Note (2) Input or I/O to output enable, Note (3) Input or I/O to output disable, Note (3) Register mode output-to-output skew Combinatorial mode output-to-output skew
Min
Max
7.5 8.5 9 9 300 400
Min
Max
10 10 10 10 300 400
Units
ns ns ns ns ps ps
Synchronous Clock Mode
Symbol
fMAX fCNT1 fCNT2 tSU1 tH tCO1 tCO2 tCNT tCL tCH tCP
EP220-7 EP224-7
EP220-10 EP224-10
Parameter
Maximum frequency (pipelined), no feedback, Note (2) Maximum counter frequency, external feedback, Note (2) Maximum counter frequency, internal feedback, Note (2) Input or I/O setup time to global clock Input or I/O hold time from global clock Global clock to output delay, Note (2) Global clock to output delay through combinatorial macrocell Minimum global clock period, Note (2) Clock low time Clock high time Clock period
Min
100 74 100 7 0
Max
Min
62.5 58.8 60.6 10 0
Max
Units
MHz MHz MHz ns ns
6.5 11 10 4 4 10 7 7 16
7 13 16.5
ns ns ns ns ns ns
Notes to tables:
(1) (2) (3)
Operating conditions: V CC = 5 V 5%, T A = 0 C to 70 C for commercial use. Measured with three I/O outputs switching. The tPZX and tPXZ parameters are measured at 0.5 V from steady-state voltage that is driven by the specified output load. The tPXZ parameter is measured with CL = 5 pF and with all eight outputs switching.
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Altera Corporation
EP220 & EP224 Classic EPLDs
Figure 6 shows the package pin-outs for EP220 and EP224 devices.
Figure 6. EP220 & EP224 Package Pin-Outs
Package outlines not drawn to scale. Windows in ceramic packages only.
INPUT/CLK
INPUT
INPUT
VCC 20
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT GND
1 2 3 4 5 6 7
20 19 18 17 16 15 14
VCC I/O I/O I/O I/O I/O I/O I/O I/O INPUT
3 INPUT INPUT INPUT INPUT INPUT 4 5 6 7 8 9 INPUT
2
1
19 18 17 16 I/O I/O I/O I/O I/O
EP220
10 GND 11 INPUT 12 I/O VCC/NC 13
8 9 10
13 12 11
20-Pin DIP
20-Pin J-Lead
INPUT/CLK
INPUT
INPUT
I/O INPUT 27 VCC
I/O 15 14
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT GND
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC INPUT I/O I/O I/O I/O I/O I/O I/O I/O
4 INPUT INPUT INPUT NC INPUT INPUT INPUT 5 6 7 8 9 10 11 12 INPUT
3
2
1
28
26 25 24 23 22 21
I/O
INPUT
GND
NC
INPUT
INPUT INPUT
24-Pin DIP
28-Pin J-Lead
Package Outlines
Refer to "Altera Device Package Outlines" in the Altera 1995 Data Book for detailed information on package outlines.
Altera Corporation
INPUT
I/O
EP220 EP224
I/O I/O I/O NC I/O I/O I/O
EP224
13 14 15 16 17
20 19 18
15
EP220 & EP224 Classic EPLDs
Product Availability
Table 2 summarizes the availability of EP220 and EP224 devices. Altera will accept Intel ordering codes for Intel devices until June 30, 1995. After that date, only Altera ordering codes will be accepted.
Table 2. EP220 & EP224 Availability
Device
EP220
Temperature Grade
Commercial temperature (0 C to 70 C)
Speed Grade
-10A -7 -10 -10A -12 -7A -10A -12 -7 -10 -12 -7 -10 -10A -12 -7A -10A -12 -7 -10
Package
20-pin CerDIP 20-pin PDIP 20-pin PDIP 20-pin PDIP 20-pin PDIP 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 24-pin PDIP 24-pin PDIP 24-pin PDIP 24-pin PDIP 28-pin PLCC 28-pin PLCC 28-pin PLCC 28-pin PLCC 28-pin PLCC
Altera Ordering Code
EP220DC-10A EP220PC-7 EP220PC-10 EP220PC-10A EP220PC-12 EP220LC-7A EP220LC-10A EP220LC-12 EP220LC-7 EP220LC-10 EP220LI-12 EP224PC-7 EP224PC-10 EP224PC-10A EP224PC-12 EP224LC-7A EP224LC-10A EP224LC-12 EP224LC-7 EP224LC-10
Intel Ordering Code
D85C220-80 P85C220-7 P85C220-10 P85C220-80 P85C220-66 N85C220-100 N85C220-80 N85C220-66 N85C220-7 N85C220-10 TN85C220-66 P85C224-7 P85C224-10 P85C224-80 P85C224-66 N85C224-100 N85C224-80 N85C224-66 N85C224-7 N85C224-10
Industrial temperature (-40 C to 85 C) EP224 Commercial temperature (0 Cto 70 C)
(R)
2610 Orchard Parkway San Jose, CA 95134-2020 (408) 894-7000 Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 894-7104 Literature Services: (408) 894-7144 16
Printed on Recycled Paper.
Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, AHDL, and FLEX 10K. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright (c) 1996 Altera Corporation. All rights reserved.
Altera Corporation

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